130 search results - page 15 / 26 » Vertical Benchmarks for CAD |
CHES
2004
Springer
15 years 5 months ago
2004
Springer
Dual-rail encoding, return-to-spacer protocol and hazard-free logic can be used to resist differential power analysis attacks by making the power consumption independent of process...
HIPC
2004
Springer
15 years 5 months ago
2004
Springer
This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to...
IFIP
1999
Springer
15 years 4 months ago
1999
Springer
In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-...
FPL
1997
Springer
15 years 3 months ago
1997
Springer
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
GLVLSI
2009
IEEE
15 years 3 months ago
2009
IEEE
Current lithography techniques use a light wavelength of 193nm to print sub-65nm features. This introduces process variations which cause mismatches between desired and actual waf...