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ISPAN
2005
IEEE
15 years 3 months ago
Process Scheduling for the Parallel Desktop
Commodity hardware and software are growing increasingly more complex, with advances such as chip heterogeneity and specialization, deeper memory hierarchies, ne-grained power ma...
Eitan Frachtenberg
ICS
2004
Tsinghua U.
15 years 3 months ago
CQoS: a framework for enabling QoS in shared caches of CMP platforms
Cache hierarchies have been traditionally designed for usage by a single application, thread or core. As multi-threaded (MT) and multi-core (CMP) platform architectures emerge and...
Ravi R. Iyer
MSS
2003
IEEE
151views Hardware» more  MSS 2003»
15 years 3 months ago
Accurate Modeling of Cache Replacement Policies in a Data Grid
Caching techniques have been used to improve the performance gap of storage hierarchies in computing systems. In data intensive applications that access large data files over wid...
Ekow J. Otoo, Arie Shoshani
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 3 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
SIGGRAPH
2000
ACM
15 years 2 months ago
Illuminating micro geometry based on precomputed visibility
Many researchers have been arguing that geometry, bump maps, and BRDFs present a hierarchy of detail that should be exploited for efficient rendering purposes. In practice howeve...
Wolfgang Heidrich, Katja Daubert, Jan Kautz, Hans-...