736 search results - page 84 / 148 » Virtual Memory: Issues of Implementation |
MICRO
2006
IEEE
15 years 4 months ago
2006
IEEE
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
74
Voted
ICC
2009
IEEE
15 years 4 months ago
2009
IEEE
—A widespread methodology for performance analysis in the field of communication systems engineering is network simulation. While ns-2 has established itself as virtually the st...
LCN
2005
IEEE
15 years 3 months ago
2005
IEEE
A combined input and crosspoint queued (CICQ) switch with a flow control latency of round-trip time (RTT) packets requires each crosspoint (CP) buffer to hold the RTT packets in o...
FPGA
2007
ACM
15 years 4 months ago
2007
ACM
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
— In deep-submicron (DSM) technology, minimizing power consumption of a bus is one of the most important design objectives in embedded system-on-chip (SoC) design. In this paper,...