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ASPDAC
2008
ACM
104views Hardware» more  ASPDAC 2008»
15 years 6 months ago
Low power clock buffer planning methodology in F-D placement for large scale circuit design
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...
Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xian...
PDPTA
2003
15 years 6 months ago
Load Balancing Voice Applications with Piranha
In this paper, we investigate the load balancing problem among a cluster of mobile and fixed devices in a voice enabled interface. We consider a design approach. The voice interfa...
Mustapha Hadim, Pierre Manneback, Michel Bagein, P...
ICDCN
2009
Springer
15 years 2 months ago
Large-Scale Networked Systems: From Anarchy to Geometric Self-structuring
Abstract. We define geometric self-structuring in a large-scale networked system as the ability of the participating nodes to collaboratively impose a geometric structure to the ne...
Anne-Marie Kermarrec, Achour Mostéfaoui, Mi...
DSN
2008
IEEE
15 years 11 months ago
A fault-tolerant directory-based cache coherence protocol for CMP architectures
Current technology trends of increased scale of integration are pushing CMOS technology into the deepsubmicron domain, enabling the creation of chips with a significantly greater...
Ricardo Fernández Pascual, José M. G...
SACMAT
2010
ACM
15 years 2 months ago
An architecture for enforcing end-to-end access control over web applications
The web is now being used as a general platform for hosting distributed applications like wikis, bulletin board messaging systems and collaborative editing environments. Data from...
Boniface Hicks, Sandra Rueda, Dave King 0002, Thom...