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1999
Tsinghua U.
15 years 6 months ago
Reducing cache misses using hardware and software page placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Timothy Sherwood, Brad Calder, Joel S. Emer
ASPLOS
1998
ACM
15 years 6 months ago
Cache-Conscious Data Placement
As the gap between memory and processor speeds continues to widen, cache efficiency is an increasingly important component of processor performance. Compiler techniques have been...
Brad Calder, Chandra Krintz, Simmi John, Todd M. A...
HIPEAC
2011
Springer
14 years 1 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem
95
Voted
SIGOPS
2008
90views more  SIGOPS 2008»
15 years 1 months ago
Virtual servers and checkpoint/restart in mainstream Linux
Virtual private servers and application checkpoint and restart are two advanced operating system features which place different but related requirements on the way kernel-provided...
Sukadev Bhattiprolu, Eric W. Biederman, Serge E. H...
113
Voted
CODES
2009
IEEE
15 years 6 months ago
A tuneable software cache coherence protocol for heterogeneous MPSoCs
In a multiprocessor system-on-chip (MPSoC) private caches introduce the cache coherence problem. Here, we target at heterogeneous MPSoCs with a network-on-chip (NoC). Existing har...
Frank E. B. Ophelders, Marco Bekooij, Henk Corpora...