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» Virtualization of Hardware - Introduction and Survey
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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 3 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi
CAV
2006
Springer
95views Hardware» more  CAV 2006»
15 years 3 months ago
Yasm: A Software Model-Checker for Verification and Refutation
Example Guided Abstraction Refinement (CEGAR) [6] framework. A number of wellengineered software model-checkers are available, e.g., SLAM [1] and BLAST [12]. Why build another one?...
Arie Gurfinkel, Ou Wei, Marsha Chechik
ASPLOS
2008
ACM
15 years 1 months ago
Improving the performance of object-oriented languages with dynamic predication of indirect jumps
Indirect jump instructions are used to implement increasinglycommon programming constructs such as virtual function calls, switch-case statements, jump tables, and interface calls...
José A. Joao, Onur Mutlu, Hyesoon Kim, Rish...
FPL
2008
Springer
153views Hardware» more  FPL 2008»
15 years 1 months ago
Exploring FPGA network on chip implementations across various application and network loads
Abstract-The network on chip will become a future general purpose interconnect for FPGAs much like today's standard OPB or PLB bus architectures. However, performance characte...
Graham Schelle, Dirk Grunwald
107
Voted
AAAI
2006
15 years 1 months ago
The Robot Intelligence Kernel
The Robot Intelligence Kernel (RIK) is a portable, reconfigurable suite of perceptual, behavioral, and cognitive capabilities that can be used across many different platforms, env...
David J. Bruemmer, Douglas A. Few, Miles C. Walton...