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ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
16 years 3 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
ICCD
2004
IEEE
138views Hardware» more  ICCD 2004»
16 years 3 months ago
A Novel Low-Power Scan Design Technique Using Supply Gating
— Reduction in test power is important to improve battery life in portable devices employing periodic self-test, to increase reliability of testing and to reduce test-cost. In sc...
Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukh...
ICCD
2003
IEEE
129views Hardware» more  ICCD 2003»
16 years 3 months ago
Reducing dTLB Energy Through Dynamic Resizing
Translation Look-aside Buffer (TLB), which is small Content Addressable Memory (CAM) structure used to translate virtual addresses to physical addresses, can consume significant ...
Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubr...
150
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ICCAD
2007
IEEE
137views Hardware» more  ICCAD 2007»
16 years 3 months ago
Combining static and dynamic defect-tolerance techniques for nanoscale memory systems
Abstract— Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a us...
Susmit Biswas, Gang Wang, Tzvetan S. Metodi, Ryan ...
SOSP
2009
ACM
16 years 3 months ago
ODR: output-deterministic replay for multicore debugging
Reproducing bugs is hard. Deterministic replay systems address this problem by providing a high-fidelity replica of an original program run that can be repeatedly executed to zer...
Gautam Altekar, Ion Stoica
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