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ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
15 years 3 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
CCE
2007
15 years 2 months ago
A Web Services based Approach for System on a Chip Design Planning
: The concept of Virtual Organisation (VO) offers various solutions to management, collaboration and coordination issues important for distributed collaborating teams. Deployment o...
Maciej Witczynski, Edward Hrynkiewicz, Adam Pawlak
FAST
2004
15 years 2 months ago
CAR: Clock with Adaptive Replacement
CLOCK is a classical cache replacement policy dating back to 1968 that was proposed as a low-complexity approximation to LRU. On every cache hit, the policy LRU needs to move the a...
Sorav Bansal, Dharmendra S. Modha
CCGRID
2010
IEEE
15 years 1 months ago
FaReS: Fair Resource Scheduling for VMM-Bypass InfiniBand Devices
In order to address the high performance I/O needs of HPC and enterprise applications, modern interconnection fabrics, such as InfiniBand and more recently, 10GigE, rely on network...
Adit Ranadive, Ada Gavrilovska, Karsten Schwan
JCST
2008
94views more  JCST 2008»
15 years 1 months ago
Runtime Engine for Dynamic Profile Guided Stride Prefetching
Stride prefetching is recognized as an important technique to improve memory access performance. The prior work usually profiles and/or analyzes the program behavior offline, and u...
Qiong Zou, Xiao-Feng Li, Long-Bing Zhang