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IPPS
2006
IEEE
15 years 10 months ago
Design flow for optimizing performance in processor systems with on-chip coarse-grain reconfigurable logic
A design flow for processor platforms with on-chip coarse-grain reconfigurable logic is presented. The reconfigurable logic is realized by a 2-Dimensional Array of Processing Elem...
Michalis D. Galanis, Grigoris Dimitroulakos, Const...
HPDC
2002
IEEE
15 years 9 months ago
A High-Performance Cluster Storage Server
An essential building block for any Data Grid infrastructure is the storage server. In this paper we describe a high-performance cluster storage server built around the SDSC Stora...
Keith Bell, Andrew A. Chien, Mario Lauria
HPDC
2002
IEEE
15 years 9 months ago
Dynamic Right-Sizing in FTP (drsFTP): Enhancing Grid Performance in User-Space
With the advent of computational grids, networking performance over the wide-area network (WAN) has become a critical component in the grid infrastructure. Unfortunately, many hig...
Mark K. Gardner, Wu-chun Feng, Mike Fisk
ICPP
1999
IEEE
15 years 8 months ago
Improving Performance of Load-Store Sequences for Transaction Processing Workloads on Multiprocessors
On-line transaction processing exhibits poor memory behavior in high-end multiprocessor servers because of complex sharing patterns and substantial interaction between the databas...
Jim Nilsson, Fredrik Dahlgren
HPCA
1997
IEEE
15 years 8 months ago
A Performance Comparison of Hierarchical Ring- and Mesh-Connected Multiprocessor Networks
This paper compares the performance of hierarchical ring- and mesh-connected wormhole routed shared memory multiprocessor networks in a simulation study. Hierarchical rings are in...
Govindan Ravindran, Michael Stumm