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HPCA
2006
IEEE
15 years 10 months ago
Software-hardware cooperative memory disambiguation
In high-end processors, increasing the number of in-flight instructions can improve performance by overlapping useful processing with long-latency accesses to the main memory. Buf...
Ruke Huang, Alok Garg, Michael C. Huang
HPCA
2003
IEEE
15 years 10 months ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
COLCOM
2007
IEEE
15 years 4 months ago
Message replication in unstructured peer-to-peer network
—Recently, unstructured peer-to-peer (P2P) applications have become extremely popular. Searching in these networks has been a hot research topic. Flooding-based searching, which ...
Osama Al-Haj Hassan, Lakshmish Ramaswamy
ICPADS
2006
IEEE
15 years 3 months ago
Loop Scheduling with Complete Memory Latency Hiding on Multi-core Architecture
The widening gap between processor and memory performance is the main bottleneck for modern computer systems to achieve high processor utilization. In this paper, we propose a new...
Chun Xue, Zili Shao, Meilin Liu, Mei Kang Qiu, Edw...
CLUSTER
2005
IEEE
15 years 3 months ago
Near Overhead-free Heterogeneous Thread-migration
Thread migration moves a single call-stack to another machine to improve either load balancing or locality. Current approaches for checkpointing and thread migration are either no...
Ronald Veldema, Michael Philippsen