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VALUETOOLS
2006
ACM
167views Hardware» more  VALUETOOLS 2006»
15 years 3 months ago
Detailed cache simulation for detecting bottleneck, miss reason and optimization potentialities
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
Jie Tao, Wolfgang Karl
SRDS
2008
IEEE
15 years 4 months ago
An Incremental File System Consistency Checker for Block-Level CDP Systems
A block-level continuous data protection (CDP) system logs every disk block update from an application server (e.g., a file or DBMS server) to a storage system so that any disk u...
Maohua Lu, Tzi-cker Chiueh, Shibiao Lin
GRID
2003
Springer
15 years 2 months ago
Faults in Grids: Why are they so bad and What can be done about it?
Computational Grids have the potential to become the main execution platform for high performance and distributed applications. However, such systems are extremely complex and pro...
Raissa Medeiros, Walfredo Cirne, Francisco Vilar B...
RTCSA
2006
IEEE
15 years 3 months ago
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors
To support high-performance and low-power for multimedia applications and for hand-held devices, embedded VLIW DSP processors are of research focus. With the tight resource constr...
Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu...
ICS
2009
Tsinghua U.
15 years 2 months ago
Dynamic task set partitioning based on balancing memory requirements to reduce power consumption
ABSTRACT Because of technology advances power consumption has emerged up as an important design issue in modern high-performance microprocessors. As a consequence, research on redu...
Diana Bautista, Julio Sahuquillo, Houcine Hassan, ...