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INFOCOM
1996
IEEE
15 years 7 months ago
Group Priority Scheduling
We present an end-to-end delay guarantee theorem for a class of guaranteed-deadline (GD) servers. The theorem can be instantiated to obtain end-to-end delay bounds for a variety of...
Simon S. Lam, Geoffrey G. Xie
RTSS
1994
IEEE
15 years 7 months ago
Bounding Worst-Case Instruction Cache Performance
The use of caches poses a difficult tradeoff for architects of real-time systems. While caches provide significant performance advantages, they have also been viewed as inherently...
Robert D. Arnold, Frank Mueller, David B. Whalley,...
ISCA
1992
IEEE
151views Hardware» more  ISCA 1992»
15 years 7 months ago
An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple Threads
In this paper, we propose a multithreaded processor architecture which improves machine throughput. In our processor architecture, instructions from different threads (not a singl...
Hiroaki Hirata, Kozo Kimura, Satoshi Nagamine, Yos...
ANCS
2007
ACM
15 years 6 months ago
Experimental evaluation of a coarse-grained switch scheduler
Modern high performance routers rely on sophisticated interconnection networks to meet ever increasing demands on capacity. Previous studies have used a combination of analysis an...
Charlie Wiseman, Jonathan S. Turner, Ken Wong, Bra...
ANCS
2007
ACM
15 years 6 months ago
Congestion management for non-blocking clos networks
We propose a distributed congestion management scheme for non-blocking, 3-stage Clos networks, comprising plain buffered crossbar switches. VOQ requests are routed using multipath...
Nikolaos Chrysos