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HIPEAC
2007
Springer
15 years 11 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
LCTRTS
2007
Springer
15 years 11 months ago
Addressing instruction fetch bottlenecks by using an instruction register file
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
Stephen Roderick Hines, Gary S. Tyson, David B. Wh...
MEMOCODE
2006
IEEE
15 years 10 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...
RTSS
2006
IEEE
15 years 10 months ago
Design of Location Service for a Hybrid Network of Mobile Actors and Static Sensors
Location services are essential to many applications running on a hybrid of wirelessly-networked mobile actors and static sensors, such as surveillance systems and the Pursuer and...
Zhigang Chen, Min Gyu Cho, Kang G. Shin
RTSS
2006
IEEE
15 years 10 months ago
Voice over Sensor Networks
Wireless sensor networks have traditionally focused on low duty-cycle applications where sensor data are reported periodically in the order of seconds or even longer. This is due ...
Rahul Mangharam, Anthony Rowe, Raj Rajkumar, Ryohe...