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CASES
2007
ACM
15 years 8 months ago
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
Rahul Nagpal, Arvind Madan, Bharadwaj Amrutur, Y. ...
CASES
2006
ACM
15 years 8 months ago
High-performance packet classification algorithm for many-core and multithreaded network processor
Packet classification is crucial for the Internet to provide more value-added services and guaranteed quality of service. Besides hardware-based solutions, many software-based cla...
Duo Liu, Bei Hua, Xianghui Hu, Xinan Tang
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CASES
2009
ACM
15 years 8 months ago
A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)
In this paper we introduce Resizable Data Composer-Cache (RDC-Cache). This novel cache architecture operates correctly at sub 500 mV in 65 nm technology tolerating large number of...
Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, F...
BSDCON
2003
15 years 6 months ago
ULE: A Modern Scheduler for FreeBSD
The existing thread scheduler in FreeBSD was well suited towards the computing environment that it was developed in. As the priorities and hardware targets of the project have cha...
Jeff Roberson
IADIS
2003
15 years 6 months ago
Using Opnet Modeler to Analyse Galileo Communication Networks
Galileo is a European initiative to develop and deploy an independent global satellite-based navigation system. It consists of a Medium Earth Orbit sat ellite constellation transm...
Filipa Borrego, Juan-Antonio Martinez Rosique, Man...