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» Voltage island-driven floorplanning
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ICCAD
2007
IEEE
144views Hardware» more  ICCAD 2007»
14 years 4 months ago
Voltage island-driven floorplanning
— Energy efficiency has become one of the most important issues to be addressed in today’s System-on-a-Chip (SoC) designs. One way to lower the power consumption is to reduce ...
Qiang Ma, Evangeline F. Y. Young
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
13 years 11 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ICCAD
2006
IEEE
110views Hardware» more  ICCAD 2006»
14 years 4 months ago
Voltage island aware floorplanning for power and timing optimization
Power consumption is a crucial concern in nanometer chip design. Researchers have shown that multiple supply voltage (MSV) is an effective method for power consumption reduction....
Wan-Ping Lee, Hung-Yi Liu, Yao-Wen Chang
ISVLSI
2006
IEEE
82views VLSI» more  ISVLSI 2006»
14 years 1 months ago
Reliability-Aware SOC Voltage Islands Partition and Floorplan
— Based on the proposed reliability characterization model, reliability-bounded low-power design as a methodology to balance reliability enhancement and power reduction in chip d...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
ASPDAC
2001
ACM
75views Hardware» more  ASPDAC 2001»
13 years 10 months ago
Integrated power supply planning and floorplanning
One of the most challenging issues in today's high-performance VLSI design is to ensure high-quality power supply to each individual circuit blocks. Reduced power supply volt...
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz...