20 search results - page 3 / 4 » Wavelet method for high-speed clock tree simulation |
89
Voted
TVLSI
2008
15 years 8 days ago
2008
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...
142
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DAC
2006
ACM
16 years 1 months ago
2006
ACM
This paper presents analysis methods for energy estimation in RC trees driven by time-varying voltage sources, e.g., buffers, timevarying power supplies, and resonant clock genera...
123
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DAC
2006
ACM
15 years 6 months ago
2006
ACM
This paper investigates methods for clock skew minimization using buffer and wire sizing. First, a technique that significantly improves solution quality and stability of sequent...
107
Voted
EURODAC
1994
IEEE
15 years 4 months ago
1994
IEEE
In performance-driven interconnect design, delay estimators are used to determine both the topology and the layout of good routing trees. We address the class of moment-matching, ...
118
Voted
TVLSI
2010
14 years 7 months ago
2010
Abstract--An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the di...