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SASP
2009
IEEE
222views Hardware» more  SASP 2009»
14 years 1 months ago
Arithmetic optimization for custom instruction set synthesis
Abstract—One of the ways that custom instruction set extensions can improve over software execution is through the use of hardware structures that have been optimized at the arit...
Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne
ERSA
2009
185views Hardware» more  ERSA 2009»
13 years 4 months ago
Woolcano: An Architecture And Tool Flow For Dynamic Instruction Set Extension On Xilinx Virtex-4 FX
In this paper, we introduce the Woolcano reconfigurable processor architecture. The architecture is based on the Xilinx Virtex-4 FX FPGA and leverages the Auxiliary Processing Uni...
Mariusz Grad, Christian Plessl
FPGA
2005
ACM
107views FPGA» more  FPGA 2005»
13 years 11 months ago
Instruction set extension with shadow registers for configurable processors
Configurable processors are becoming increasingly popular for modern embedded systems (especially for the field-programmable system-on-a-chip). While steady progress has been made...
Jason Cong, Yiping Fan, Guoling Han, Ashok Jaganna...
CHES
2009
Springer
150views Cryptology» more  CHES 2009»
14 years 1 months ago
A Design Flow and Evaluation Framework for DPA-Resistant Instruction Set Extensions
Power-based side channel attacks are a significant security risk, especially for embedded applications. To improve the security of such devices, protected logic styles have been p...
Francesco Regazzoni, Alessandro Cevrero, Fran&cced...
DATE
2005
IEEE
109views Hardware» more  DATE 2005»
13 years 12 months ago
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement
Customization of processor architectures through Instruction Set Extensions (ISEs) is an effective way to meet the growing performance demands of embedded applications. A high-qua...
Partha Biswas, Sudarshan Banerjee, Nikil D. Dutt, ...