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CIDR
2007
173views Algorithms» more  CIDR 2007»
15 years 3 months ago
Database Servers on Chip Multiprocessors: Limitations and Opportunities
Prior research shows that database system performance is dominated by off-chip data stalls, resulting in a concerted effort to bring data into on-chip caches. At the same time, hi...
Nikos Hardavellas, Ippokratis Pandis, Ryan Johnson...
EUROSYS
2007
ACM
15 years 11 months ago
Thread clustering: sharing-aware scheduling on SMP-CMP-SMT multiprocessors
The major chip manufacturers have all introduced chip multiprocessing (CMP) and simultaneous multithreading (SMT) technology into their processing units. As a result, even low-end...
David K. Tam, Reza Azimi, Michael Stumm
ISCA
1999
IEEE
90views Hardware» more  ISCA 1999»
15 years 6 months ago
Correlated Load-Address Predictors
As microprocessors become faster, the relative performance cost of memory accesses increases. Bigger and faster caches significantly reduce the absolute load-to-use time delay. Ho...
Michael Bekerman, Stéphan Jourdan, Ronny Ro...
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
15 years 10 months ago
Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache
Abstract-- We deconstruct and compare the two dominant existing approaches for L1 data cache (L1D) error protection, with respect to performance, L2 cache bandwidth, power, and are...
Nathan Sadler, Daniel Sorin
DSD
2007
IEEE
132views Hardware» more  DSD 2007»
15 years 5 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge