488 search results - page 24 / 98 » Weighted Logics for Traces |
VTS
2000
IEEE
15 years 4 months ago
2000
IEEE
ESIM is a simulation tool that integrates logic fault and design error simulation for logic circuits. It targets several design error and fault models, and uses a novel mix of sim...
IEEEMSP
2002
IEEE
15 years 4 months ago
2002
IEEE
–This paper is an experimental study on the performance of the two major methods for macro-level similarity measurement: linear weighted merging and logical retrieval. Performanc...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
System level modeling with executable languages such as C/C++ has been crucial in the development of large electronic systems from general processors to application specific desig...
101
click to vote
LISP
2008
14 years 11 months ago
2008
Abstract. Tracing computations is a widely used methodology for program debugging. Lazy languages, however, pose new demands on tracing techniques because following the actual trac...
TVLSI
2010
14 years 6 months ago
2010
Hardware debuggers and logic analyzers must be able to record a continuous trace of data. Since the trace data are tremendous, to save space, these traces are often compressed. The...