488 search results - page 38 / 98 » Weighted Logics for Traces |
FORMATS
2007
Springer
15 years 6 months ago
2007
Springer
Abstract. In this paper we describe AMT, a tool for monitoring temporal properties of continuous signals. We first introduce STL/PSL, a specification formalism based on the indus...
HASE
2005
IEEE
15 years 5 months ago
2005
IEEE
Checking various temporal requirements is a key dependability concern in safety-critical systems. As modelchecking approaches do not scale well to systems of high complexity the r...
CONCUR
2006
Springer
15 years 3 months ago
2006
Springer
Impossible futures equivalence is the semantic equivalence on labelled transition systems that identifies systems iff they have the same "AGEF" properties: temporal logic...
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ASE
2005
14 years 11 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...
ICCAD
2007
IEEE
15 years 8 months ago
2007
IEEE
Late CMOS scaling reduces device reliability, and existing work has studied the permanent SER (soft error rate) for configuration memory in FPGA extensively. In this paper, we sh...