338 search results - page 2 / 68 » What is Input Output Logic |
DATE
2010
IEEE
15 years 5 months ago
2010
IEEE
— This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the conc...
PATMOS
2005
Springer
15 years 5 months ago
2005
Springer
The time taken for a CMOS logic gate output to change after one or more inputs have changed is called the output delay of the gate. A conventional multi-input CMOS gate is designed...
91
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ASPDAC
2006
ACM
15 years 6 months ago
2006
ACM
This paper introduces a new current-based cell timing analyzer, called CGTA, which has a higher performance than existing logic cell timing analysis tools. CGTA relies on a compac...
101
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DDECS
2009
IEEE
15 years 7 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
DATE
1999
IEEE
15 years 4 months ago
1999
IEEE
The objective of this paper is to define a minimum number of configurations for testing the configurable modules that interface the global interconnect and the logic cells of SRAM...