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VMCAI
2005
Springer
15 years 3 months ago
On the Complexity of Error Explanation
When a system fails to satisfy its specification, the model checker produces an error trace (or counter-example) that demonstrates an undesirable behavior, which is then used in d...
Nirman Kumar, Viraj Kumar, Mahesh Viswanathan
FASE
2009
Springer
15 years 4 months ago
Reducing the Costs of Bounded-Exhaustive Testing
Abstract. Bounded-exhaustive testing is an automated testing methodology that checks the code under test for all inputs within given bounds: first the user describes a set of test...
Vilas Jagannath, Yun Young Lee, Brett Daniel, Dark...
TCAD
2008
114views more  TCAD 2008»
14 years 9 months ago
Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
Himanshu Jain, Daniel Kroening, Natasha Sharygina,...
CONCUR
2010
Springer
14 years 10 months ago
On the Compositionality of Round Abstraction
ompositionality of Round Abstraction Abstract Dan R. Ghica and Mohamed N. Menaa University of Birmingham, U.K. We revisit a technique called round abstraction as a solution to the ...
Dan R. Ghica, Mohamed N. Menaa
FMCAD
2008
Springer
14 years 11 months ago
Word-Level Sequential Memory Abstraction for Model Checking
el Sequential Memory Abstraction for Model Checking Per Bjesse Advanced Technology Group Synopsys Inc. Many designs intermingle large memories with wide data paths and nontrivial c...
Per Bjesse