1299 search results - page 239 / 260 » Why Not Use a Pattern-Based Parallel Programming System |
IEEEPACT
2008
IEEE
15 years 8 months ago
2008
IEEE
In a hardware transactional memory system with lazy versioning and lazy conflict detection, the process of transaction commit can emerge as a bottleneck. This is especially true ...
137
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ISHPC
1999
Springer
15 years 6 months ago
1999
Springer
On-chip multiprocessor can be an alternative to the wide-issue superscalar processor approach which is currently the mainstream to exploit the increasing number of transistors on ...
CLUSTER
2009
IEEE
15 years 9 months ago
2009
IEEE
Abstract—Multi-core systems are now extremely common in modern clusters. In the past commodity systems may have had up to two or four CPUs per compute node. In modern clusters, t...
115
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CANPC
1999
Springer
15 years 6 months ago
1999
Springer
Streamlining communication is key to achieving good performance in shared-memory parallel programs. While full hardware support for cache coherence generally offers the best perfo...
139
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MICRO
2010
IEEE
15 years 16 days ago
2010
IEEE
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...