499 search results - page 46 / 100 » Wire shaping is practical |
ISVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
The “chicken-egg” dilemma between VLSI interconnect timing optimization and delay calculation suggests an iterative approach. We separate interconnect timing transformation as...
LCN
2003
IEEE
15 years 5 months ago
2003
IEEE
Studies of mobile ad-hoc networks are often based on simulation and their underlying, necessarily simplified assumptions of physical reality. In order to analyse the practical pro...
SLIP
2003
ACM
15 years 5 months ago
2003
ACM
Aggressive process scaling and increasing clock rates have made crosstalk noise an important issue in VLSI design. Switching on adjacent wires on long bus lines can increase delay...
SACRYPT
2001
Springer
15 years 4 months ago
2001
Springer
Abstract. Inthis paper we present several weaknesses in the keyscheduling algorithm of RC4, and describe their cryptanalytic signi cance. We identify a large number of weak keys, i...
DATE
2004
IEEE
15 years 3 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...