25 search results - page 2 / 5 » Wire sizing with scattering effect for nanoscale interconnec... |
ICCAD
2002
IEEE
14 years 3 months ago
2002
IEEE
As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. ...
INTEGRATION
2007
13 years 6 months ago
2007
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tap...
VLSISP
2008
13 years 6 months ago
2008
Each new semiconductor technology node brings smaller, faster transistors and smaller, slower wires. In particular, long interconnect wires in modern FPGAs now require rebuffering ...
ISQED
2002
IEEE
13 years 11 months ago
2002
IEEE
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
TVLSI
2008
13 years 6 months ago
2008
Abstract--A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pa...