94 search results - page 18 / 19 » Wire width planning for interconnect performance optimizatio... |
DAC
2005
ACM
14 years 7 months ago
2005
ACM
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
IJES
2008
13 years 6 months ago
2008
: On-chipimplementationofmultiprocessorsystemsneedstoplanarisetheinterconnect networks onto the silicon floorplan. Compared with traditional ASIC/SoC architectures, Multiprocessor ...
DAC
2002
ACM
14 years 7 months ago
2002
ACM
The design of high-throughput large-state Viterbi decoders relies on the use of multiple arithmetic units. The global communication channels among these parallel processors often ...
CN
2006
13 years 6 months ago
2006
In this paper, we address the server selection problem for streaming applications on the Internet. The architecture we consider is similar to the content distribution networks con...
ISLPED
2010
ACM
13 years 4 months ago
2010
ACM
In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-...