564 search results - page 16 / 113 » Wireplanning in logic synthesis |
116
click to vote
TC
2011
14 years 6 months ago
2011
—Mounting concerns over variability, defects and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signa...
125
click to vote
DEDS
2000
14 years 11 months ago
2000
In this paper, we present the integration of controller synthesis techniques in the SIGNAL environment through the description of a tool dedicated to the incremental construction o...
146
click to vote
FCCM
2011
IEEE
14 years 3 months ago
2011
IEEE
— Recent progress in High-Level Synthesis (HLS) es has helped raise the abstraction level of FPGA programming. However implementation and performance evaluation of the HLS-genera...
DAC
2005
ACM
15 years 1 months ago
2005
ACM
This paper presents a novel synthesis algorithm that reduces the area needed for implementing multiplexers on an FPGA by an average of 18%. This is achieved by reducing the number...
FPGA
2005
ACM
15 years 5 months ago
2005
ACM
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures. Our method transforms sequential programs as well as high-leve...