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» Wireplanning in logic synthesis
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VTS
1996
IEEE
111views Hardware» more  VTS 1996»
15 years 1 months ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey
VLDB
1990
ACM
143views Database» more  VLDB 1990»
15 years 1 months ago
Synthesizing Database Transactions
Database programming requires having the knowledge of database semantics both to maintain database integrity and to explore more optimization opportunities. Automated programming ...
Xiaolei Qian
POPL
2010
ACM
15 years 7 months ago
A Relational Modal Logic for Higher-Order Stateful ADTs
The method of logical relations is a classic technique for proving the equivalence of higher-order programs that implement the same observable behavior but employ different intern...
Derek Dreyer, Georg Neis, Andreas Rossberg, Lars B...
DAC
2006
ACM
15 years 10 months ago
Synthesis of high-performance packet processing pipelines
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the featur...
Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
FM
1999
Springer
121views Formal Methods» more  FM 1999»
15 years 2 months ago
Incremental Design of a Power Transformer Station Controller Using a Controller Synthesis Methodology
ÐIn this paper, we describe the incremental specification of a power transformer station controller using a controller synthesis methodology. We specify the main requirements as s...
Hervé Marchand, Mazen Samaan