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» Wireplanning in logic synthesis
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TCS
2008
14 years 9 months ago
Temporal constraints in the logical analysis of regulatory networks
Starting from the logical description of gene regulatory networks developed by R. Thomas, we introduce an enhanced modelling approach based on timed automata. We obtain a refined ...
Heike Siebert, Alexander Bockmayr
ICCAD
2007
IEEE
118views Hardware» more  ICCAD 2007»
15 years 6 months ago
Timing variation-aware high-level synthesis
—This work proposes a new yield computation technique dedicated to HLS, which is an essential component in timing variationaware HLS research field. The SSTAs used by the curren...
Jongyoon Jung, Taewhan Kim
ICCAD
2008
IEEE
133views Hardware» more  ICCAD 2008»
15 years 6 months ago
Module locking in biochemical synthesis
—We are developing a framework for computation with biochemical reactions with a focus on synthesizing specific logical functionality, a task analogous to technology-independent...
Brian Fett, Marc D. Riedel
ADBIS
2005
Springer
120views Database» more  ADBIS 2005»
15 years 3 months ago
Extensible Canonical Process Model Synthesis Applying Formal Interpretation
The current period of IT development is characterized by an explosive growth of diverse information representation languages. Applying integration and composition of heterogeneous ...
Leonid A. Kalinichenko, Sergey A. Stupnikov, Nikol...
ICCAD
2006
IEEE
127views Hardware» more  ICCAD 2006»
15 years 6 months ago
Platform-based resource binding using a distributed register-file microarchitecture
Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based ...
Jason Cong, Yiping Fan, Wei Jiang