564 search results - page 62 / 113 » Wireplanning in logic synthesis |
114
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AGP
2010
IEEE
15 years 1 months ago
2010
IEEE
We present an overview of the program transformation techniques which have been proposed over the past twenty-five years in the context of logic programming. We consider the appro...
DAC
2006
ACM
15 years 10 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
FPL
2009
Springer
15 years 2 months ago
2009
Springer
We leverage properties of the logic synthesis netlist to define both a logic element architecture and an associated technology mapping algorithm that together provide improved lo...
124
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ICCS
2007
Springer
15 years 1 months ago
2007
Springer
Abstract. Sensing is at the core of virtually every DDDAS application. Sensing applications typically involve distributed communication and coordination over large self-organized n...
GLVLSI
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...