564 search results - page 71 / 113 » Wireplanning in logic synthesis |
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
We define a robust fault model as a model where the existence of an undetectable fault implies the existence of logic redundancy, or more generally, a suboptimality in the synthe...
JELIA
2004
Springer
15 years 3 months ago
2004
Springer
Biochemical pathways or networks are generic representations used to model many different types of complex functional and physical interactions in biological systems. Models based ...
FPL
2000
Springer
15 years 1 months ago
2000
Springer
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standa...
INTEGRATION
2006
14 years 9 months ago
2006
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible ...
ICCAD
2003
IEEE
15 years 6 months ago
2003
IEEE
In the context of physical synthesis, large-scale standard-cell placement algorithms must facilitate incremental changes to layout, both local and global. In particular, flexible...