564 search results - page 89 / 113 » Wireplanning in logic synthesis |
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Structuring and mapping of a Boolean function is an important problem in the design of complex integrated circuits. Libraryaware constructive decomposition offers a solution to th...
124
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
76
Voted
ICCAD
2006
IEEE
15 years 6 months ago
2006
IEEE
The paper explores several ways to improve the speed and capacity of combinational equivalence checking based on Boolean satisfiability (SAT). State-of-the-art methods use simulat...
ICCAD
2004
IEEE
15 years 6 months ago
2004
IEEE
— This paper presents Hermes, a depth-optimal LUT based FPGA mapping algorithm. The presented algorithm is based on a new strategy for finding LUTs allowing to find a good LUT ...
57
Voted
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—We investigate restructuring techniques based on decomposition/factorization, with the objective to move critical signals toward the output while minimizing area. A specific ap...