Sciweavers

85 search results - page 17 / 17
» Wiring edge-disjoint layouts
Sort
View
DAC
2005
ACM
14 years 7 months ago
Multilevel full-chip routing for the X-based architecture
As technology advances into the nanometer territory, the interconnect delay has become a first-order effect on chip performance. To handle this effect, the X-architecture has been...
Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-J...
ICCAD
2006
IEEE
123views Hardware» more  ICCAD 2006»
14 years 3 months ago
A network-flow approach to timing-driven incremental placement for ASICs
We present a novel incremental placement methodology called FlowPlace for significantly reducing critical path delays of placed standard-cell circuits. FlowPlace includes: a) a t...
Shantanu Dutt, Huan Ren, Fenghua Yuan, Vishal Suth...
IPPS
2000
IEEE
13 years 10 months ago
Connectivity Models for Optoelectronic Computing Systems
Abstract. Rent's rule and related concepts of connectivity such as dimensionality, line-length distributions, and separators have found great use in fundamental studies of di ...
Haldun M. Özaktas
DOCENG
2007
ACM
13 years 10 months ago
SALT: a semantic approach for generating document representations
The structure of a document has an important influence on the perception of its content. Considering scientific publications, we can affirm that by making use of the ordinary line...
Tudor Groza, Alexander Schutz, Siegfried Handschuh
JOIN
2007
96views more  JOIN 2007»
13 years 6 months ago
Universal Routing and Performance Assurance for Distributed Networks
In this paper, we show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. W...
Kevin F. Chen, Edwin Hsing-Mean Sha