85 search results - page 3 / 17 » Wiring edge-disjoint layouts |
DAC
1999
ACM
15 years 2 months ago
1999
ACM
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
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Voted
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
— This paper suggests a methodology to decrease the power of a static CMOS standard cell design at layout level by focusing on switched capacitance. The term switched is the key:...
DAC
2012
ACM
13 years 2 days ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
ESANN
2008
14 years 11 months ago
2008
Recent papers by D. Chklovskii and E.M. Izhikevich suggest that wiring costs may play a significant role in the physical layout and function of neuronal structures. About eighty ye...