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VLSID
2003
IEEE
115views VLSI» more  VLSID 2003»
15 years 11 months ago
An Adaptive Supply-Voltage Scheme for Low Power Self-Timed CMOS Digital Design
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
W. Kuang, J. S. Yuan
VLDB
2006
ACM
162views Database» more  VLDB 2006»
15 years 11 months ago
Dependency trees in sub-linear time and bounded memory
We focus on the problem of efficient learning of dependency trees. Once grown, they can be used as a special case of a Bayesian network, for PDF approximation, and for many other u...
Dan Pelleg, Andrew W. Moore
EWSN
2006
Springer
15 years 10 months ago
Results of Bit Error Measurements with Sensor Nodes and Casuistic Consequences for Design of Energy-Efficient Error Control Sche
For the proper design of energy-efficient error control schemes some insight into channel error patterns is needed. This paper presents bit error and packet loss measurements taken...
Andreas Willig, Robert Mitschke
ICCD
2006
IEEE
84views Hardware» more  ICCD 2006»
15 years 8 months ago
Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation
—X-filling is preferred for low-capture-power scan test generation, since it reduces IR-drop-induced yield loss without the need of any circuit modification. However, the effecti...
Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Y...
ICCD
2004
IEEE
103views Hardware» more  ICCD 2004»
15 years 8 months ago
A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network
This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to...
Yi Zou, Yici Cai, Qiang Zhou, Xianlong Hong, Sheld...