Sciweavers

6202 search results - page 187 / 1241
» Without Loss of Generality
Sort
View
ISLPED
1997
ACM
104views Hardware» more  ISLPED 1997»
15 years 8 months ago
Composite sequence compaction for finite-state machines using block entropy and high-order Markov models
- The objective of this paper is to provide an effective technique for accurate modeling of the external input sequences that affect the behavior of Finite State Machines (FSMs). B...
Radu Marculescu, Diana Marculescu, Massoud Pedram
ISCA
1991
IEEE
110views Hardware» more  ISCA 1991»
15 years 8 months ago
Dynamic Base Register Caching: A Technique for Reducing Address Bus Width
When address reference streams exhibit high degrees of spatial and temporal locality, many of the higher order address lines carry redundant information. By caching the higher ord...
Matthew K. Farrens, Arvin Park
CF
2008
ACM
15 years 7 months ago
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components--including registers, function...
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, ...
ASPDAC
2005
ACM
81views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Standard CMOS technology on-chip inductors with pn junctions substrate isolation
New substrate isolation structures using pattern stacked pn junctions for on-chip inductors in standard CMOS technology are presented. For the first time, through increasing the re...
Hongyan Jian, Zhangwen Tang, Jie He, Jinglan He, M...
ASPDAC
2005
ACM
131views Hardware» more  ASPDAC 2005»
15 years 7 months ago
Analysis of buffered hybrid structured clock networks
- This paper presents a novel approach for fast transient analysis of buffered hybrid structured clock networks. The new method applies structure reduction and relaxed hierarchical...
Yi Zou, Qiang Zhou, Yici Cai, Xianlong Hong, Sheld...