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DATE
2003
IEEE
97views Hardware» more  DATE 2003»
15 years 3 months ago
Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation
Instruction reuse is a microarchitectural technique that improves the execution time of a program by removing redundant computations at run-time. Although this is the job of an op...
G. Surendra, Subhasis Banerjee, S. K. Nandy
DATE
2010
IEEE
165views Hardware» more  DATE 2010»
15 years 2 months ago
Multicore soft error rate stabilization using adaptive dual modular redundancy
— The use of dynamic voltage and frequency scaling (DVFS) in contemporary multicores provides significant protection from unpredictable thermal events. A side effect of DVFS can ...
Ramakrishna Vadlamani, Jia Zhao, Wayne P. Burleson...
TPHOL
1994
IEEE
15 years 1 months ago
Trustworthy Tools for Trustworthy Programs: A Verified Verification Condition Generator
Verification Condition Generator (VCG) tools have been effective in simplifying the task of proving programs correct. However, in the past these VCG tools have in general not thems...
Peter V. Homeier, David F. Martin
LOPSTR
1992
Springer
15 years 1 months ago
Logimix: A Self-Applicable Partial Evaluator for Prolog
We present a self-applicable partial evaluator for a large subset of full Prolog. The partial evaluator, called Logimix, is the result of applying our experience from partial eval...
Torben Æ. Mogensen, Anders Bondorf
CGO
2004
IEEE
15 years 1 months ago
Probabilistic Predicate-Aware Modulo Scheduling
Predicated execution enables the removal of branches by converting segments of branching code into sequences of conditional operations. An important side effect of this transforma...
Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Da...