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» Word-Level Sequential Memory Abstraction for Model Checking
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GLOBECOM
2007
IEEE
15 years 3 months ago
A Bit-Node Centric Architecture for Low-Density Parity-Check Decoders
Abstract—A bit-node centric decoder architecture for lowdensity parity-check codes is proposed. This architecture performs the optimum sum-product algorithm. A bit node processin...
Ruwan N. S. Ratnayake, Erich F. Haratsch, Gu-Yeon ...
KBSE
2007
IEEE
15 years 3 months ago
Model checking concurrent linux device drivers
toolkit demonstrates that predicate abstraction enables automated verification of real world Windows device Our predicate abstraction-based tool DDVerify enables the automated ve...
Thomas Witkowski, Nicolas Blanc, Daniel Kroening, ...
SPAA
2005
ACM
15 years 3 months ago
Efficient algorithms for verifying memory consistency
One approach in verifying the correctness of a multiprocessor system is to show that its execution results comply with the memory consistency model it is meant to implement. It ha...
Chaiyasit Manovit, Sudheendra Hangal
FMSD
2006
85views more  FMSD 2006»
14 years 9 months ago
Distributed disk-based algorithms for model checking very large Markov chains
In this paper we present data structures and distributed algorithms for CSL model checking-based performance and dependability evaluation. We show that all the necessary computatio...
Alexander Bell, Boudewijn R. Haverkort
KBSE
2008
IEEE
15 years 3 months ago
Unit Testing of Flash Memory Device Driver through a SAT-Based Model Checker
Flash memory has become virtually indispensable in most mobile devices. In order for mobile devices to successfully provide services to users, it is essential that flash memory b...
Moonzoo Kim, Yunho Kim, Hotae Kim