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SECON
2007
IEEE
15 years 4 months ago
Log-normal shadowing meets SINR: A numerical study of Capacity in Wireless Networks
— The capacity of wireless multi-hop networks has been studied extensively in recent years. Most existing work tackles the problem from an asymptotic perspective and assumes a si...
Patrick Stuedi, Gustavo Alonso
IJNSEC
2007
137views more  IJNSEC 2007»
14 years 9 months ago
An FPGA-based AES-CCM Crypto Core For IEEE 802.11i Architecture
The widespread adoption of IEEE 802.11 wireless networks has brought its security paradigm under active research. One of the important research areas in this field is the realiza...
Arshad Aziz, Nassar Ikram
DAC
2006
ACM
15 years 10 months ago
Rapid estimation of control delay from high-level specifications
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
Gagan Raj Gupta, Madhur Gupta, Preeti Ranjan Panda
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
15 years 3 months ago
Impact of Gate-Length Biasing on Threshold-Voltage Selection
Gate-length biasing is a runtime leakage reduction technique that leverages on the short-channel effect by marginally increasing the gate-length of MOS devices to significantly ...
Andrew B. Kahng, Swamy Muddu, Puneet Sharma
FPL
2005
Springer
114views Hardware» more  FPL 2005»
15 years 3 months ago
Post-Placement BDD-Based Decomposition for FPGAs
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
Valavan Manohararajah, Deshanand P. Singh, Stephen...