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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 6 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
HPCA
2008
IEEE
15 years 10 months ago
PEEP: Exploiting predictability of memory dependences in SMT processors
Simultaneous Multithreading (SMT) attempts to keep a dynamically scheduled processor's resources busy with work from multiple independent threads. Threads with longlatency st...
Samantika Subramaniam, Milos Prvulovic, Gabriel H....
IAJIT
2011
14 years 1 months ago
Network load and packet loss optimization during handoff using multi-scan approach
: Handoff is a critical function that enables mobile nodes to stay connected to the wireless network by switching the data connection from one WLAN to another. During handoff the c...
Anwar Saif, Mohammed Othman
IMC
2004
ACM
15 years 3 months ago
Bandwidth estimation in broadband access networks
There has been much work on developing techniques for estimating the capacity and the available bandwidth of network paths based on end-point measurements. The focus has primarily...
Karthik Lakshminarayanan, Venkata N. Padmanabhan, ...
AAAI
1997
14 years 11 months ago
Case and Constraint-Based Apartment Construction Project Planning System: FASTrak-APT
To effectively generate a fast and consistent apartment construction project network, Hyundai and KAIST have developed a case and constraint based project planning expert system f...
Kyoung Jun Lee, Hyun Woo Kim, Jae Kyu Lee, Tae Hwa...