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ISCA
2009
IEEE
152views Hardware» more  ISCA 2009»
15 years 10 months ago
Scaling the bandwidth wall: challenges in and avenues for CMP scaling
As transistor density continues to grow at an exponential rate in accordance to Moore’s law, the goal for many Chip Multi-Processor (CMP) systems is to scale the number of on-ch...
Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken...
141
Voted
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
15 years 10 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...
ICDM
2008
IEEE
141views Data Mining» more  ICDM 2008»
15 years 10 months ago
Scalable Tensor Decompositions for Multi-aspect Data Mining
Modern applications such as Internet traffic, telecommunication records, and large-scale social networks generate massive amounts of data with multiple aspects and high dimensiona...
Tamara G. Kolda, Jimeng Sun
121
Voted
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
15 years 10 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
145
Voted
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
15 years 9 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski