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137
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CDES
2008
90views Hardware» more  CDES 2008»
15 years 5 months ago
Nanocompilation for the Cell Matrix Architecture
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
Thomas Way, Rushikesh Katikar, Ch. Purushotham
142
Voted
BNCOD
1997
111views Database» more  BNCOD 1997»
15 years 5 months ago
Improved and Optimized Partitioning Techniques in Database Query Processing
Abstract. In this paper we present two improvements to the partitioning process: 1) A new dynamic bu er management strategy is employed to increase the average block size of I/O-tr...
Kjell Bratbergsengen, Kjetil Nørvåg
119
Voted
PPL
2007
126views more  PPL 2007»
15 years 3 months ago
Challenges in Parallel Graph Processing
Graph algorithms are becoming increasingly important for solving many problems in scientific computing, data mining and other domains. As these problems grow in scale, parallel c...
Andrew Lumsdaine, Douglas Gregor, Bruce Hendrickso...
126
Voted
ERSA
2009
109views Hardware» more  ERSA 2009»
15 years 1 months ago
An Implementation of Security Extensions for Data Integrity and Confidentiality in Soft-Core Processors
An increasing number of embedded system solutions in space, military, and consumer electronics applications rely on processor cores inside reconfigurable logic devices. Ensuring da...
Austin Rogers, Aleksandar Milenkovic
117
Voted
MJ
2008
111views more  MJ 2008»
15 years 3 months ago
CMOL: Second life for silicon
This report is a brief review of the recent work on architectures for the prospective hybrid CMOS/nanowire/ nanodevice ("CMOL") circuits including digital memories, reco...
Konstantin K. Likharev