Sciweavers

2035 search results - page 358 / 407
» Working memory
Sort
View
JAIR
2008
171views more  JAIR 2008»
14 years 11 months ago
AND/OR Multi-Valued Decision Diagrams (AOMDDs) for Graphical Models
Inspired by AND/OR search spaces for graphical models recently introduced, we propose to augment Multi-Valued Decision Diagrams (MDD) with AND nodes, in order to capture function ...
Robert Mateescu, Rina Dechter, Radu Marinescu 0002
ISCA
2008
IEEE
114views Hardware» more  ISCA 2008»
15 years 6 months ago
Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks
Future chip multiprocessors (CMPs) may have hundreds to thousands of threads competing to access shared resources, and will require quality-of-service (QoS) support to improve sys...
Jae W. Lee, Man Cheuk Ng, Krste Asanovic
ISCA
1995
IEEE
120views Hardware» more  ISCA 1995»
15 years 3 months ago
Streamlining Data Cache Access with Fast Address Calculation
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...
Todd M. Austin, Dionisios N. Pnevmatikatos, Gurind...
ICCAD
2008
IEEE
170views Hardware» more  ICCAD 2008»
15 years 8 months ago
Obstacle-avoiding rectilinear Steiner tree construction
— In today’s VLSI designs, there can be many blockages in a routing region. The obstacle-avoiding rectilinear Steiner minimum tree (OARSMT) problem has become an important prob...
Liang Li, Evangeline F. Y. Young
JACM
2000
77views more  JACM 2000»
14 years 11 months ago
The fault span of crash failures
A crashing network protocol is an asynchronous protocol whose memory does not survive crashes. We show that a crashing network protocol that works over unreliable links can be driv...
George Varghese, Mahesh Jayaram