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DSD
2010
IEEE
162views Hardware» more  DSD 2010»
15 years 1 months ago
A Parallel for Loop Memory Template for a High Level Synthesis Compiler
—We propose a parametrized memory template for applications with parallel for loops. The template’s parameters reflect important trade-offs made during system design. The temp...
Craig Moore, Wim Meeus, Harald Devos, Dirk Strooba...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
15 years 7 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...
111
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ISPASS
2005
IEEE
15 years 8 months ago
Balancing Performance and Reliability in the Memory Hierarchy
Cosmic-ray induced soft errors in cache memories are becoming a major threat to the reliability of microprocessor-based systems. In this paper, we present a new method to accurate...
Hossein Asadi, Vilas Sridharan, Mehdi Baradaran Ta...
PVG
2003
IEEE
138views Visualization» more  PVG 2003»
15 years 8 months ago
Sort-First, Distributed Memory Parallel Visualization and Rendering
While commodity computing and graphics hardware has increased in capacity and dropped in cost, it is still quite difficult to make effective use of such systems for general-purpos...
E. Wes Bethel, Greg Humphreys, Brian E. Paul, J. D...
ICNSC
2007
IEEE
15 years 9 months ago
Associative Memory for Noisy and Structurally Deformed Two-Dimensional Images Using Neural Networks
—This paper studies the problem of understanding noisy and structurally deformed two-dimensional images by means of abstractly defined neural works. First, in the framework of sy...
Hiroshi Inaba, Tomoki Takahashi, Keylan Alimhan