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FPL
2005
Springer
140views Hardware» more  FPL 2005»
15 years 8 months ago
A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs
This paper presents a configuration memory architecture that offers fast FPGA reconfiguration. The underlying principle behind the design is the use of fine-grained partial rec...
Usama Malik, Oliver Diessel
DAC
1997
ACM
15 years 7 months ago
Remembrance of Things Past: Locality and Memory in BDDs
Binary Decision Diagrams BDDs are e cient at manipulating large sets in a compact manner. BDDs, however, are inefcient at utilizing the memory hierarchy of the computer. Recent ...
Srilatha Manne, Dirk Grunwald, Fabio Somenzi
POPL
2009
ACM
16 years 3 months ago
The semantics of x86-CC multiprocessor machine code
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consistent memory that is assumed by most work on semantics and verification. Instead, t...
Susmit Sarkar, Peter Sewell, Francesco Zappa Narde...
EUROPAR
2005
Springer
15 years 8 months ago
A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors
There are two important hurdles that restrict the scalability of directory-based shared-memory multiprocessors: the directory memory overhead and the long L2 miss latencies due to ...
Alberto Ros, Manuel E. Acacio, José M. Garc...
HIPC
2007
Springer
15 years 9 months ago
Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors
Traditional directory-based cache coherence protocols suffer from long-latency cache misses as a consequence of the indirection introduced by the home node, which must be accessed...
Alberto Ros, Manuel E. Acacio, José M. Garc...