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ISCAS
2002
IEEE
124views Hardware» more  ISCAS 2002»
15 years 8 months ago
Performance optimization of multiple memory architectures for DSP
Multiple memory module architecture offers higher performance by providing potentially doubled memory bandwidth. Two key problems in gaining high performance in this kind of archi...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha
HPCC
2009
Springer
15 years 7 months ago
A Quantitative Study of Memory System Interference in Chip Multiprocessor Architectures
—The potential for destructive interference between running processes is increased as Chip Multiprocessors (CMPs) share more on-chip resources. We believe that understanding the ...
Magnus Jahre, Marius Grannæs, Lasse Natvig
GECCO
2006
Springer
123views Optimization» more  GECCO 2006»
15 years 6 months ago
The parallel Nash Memory for asymmetric games
Coevolutionary algorithms search for test cases as part of the search process. The resulting adaptive evaluation function takes away the need to define a fixed evaluation function...
Frans A. Oliehoek, Edwin D. de Jong, Nikos A. Vlas...
ASPLOS
1991
ACM
15 years 6 months ago
NUMA Policies and Their Relation to Memory Architecture
Multiprocessor memory reference traces provide a wealth of information on the behavior of parallel programs. We have used this information to explore the relationship between kern...
William J. Bolosky, Michael L. Scott, Robert P. Fi...
SCP
2008
144views more  SCP 2008»
15 years 2 months ago
Implicit ownership types for memory management
Abstract. The Real-time Specification for Java (RTSJ) introduced a range of language features for explicit memory management. While the RTSJ gives programmers fine control over mem...
Tian Zhao, Jason Baker, James Hunt, James Noble, J...