2035 search results - page 82 / 407 » Working memory |
130
click to vote
DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
In a parallel system with multiple CPUs, one of the key problems is to assign loop iterations to processors. This problem, known as the loop scheduling problem, has been studied i...
121
click to vote
DATE
2007
IEEE
15 years 9 months ago
2007
IEEE
Partitioning a memory into multiple blocks that can be independently accessed is a widely used technique to reduce its dynamic power. For embedded systems, its benefits can be ev...
137
click to vote
IEEECIT
2010
IEEE
15 years 1 months ago
2010
IEEE
There are two avenues for many-core machines to gain higher performance: increasing the number of processors, and increasing the number of vector units in one SIMD processor. A tru...
129
click to vote
ISCA
2009
IEEE
15 years 9 months ago
2009
IEEE
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
153
click to vote
NOCS
2008
IEEE
15 years 9 months ago
2008
IEEE
We present a methodology to debug a SOC by concentrating on its communication. Our extended communication model includes a) multiple signal groups per interface protocol at each I...