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MICRO
2007
IEEE
129views Hardware» more  MICRO 2007»
15 years 9 months ago
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy
Current on-chip block-centric memory hierarchies exploit access patterns at the fine-grain scale of small blocks. Several recently proposed techniques for coherence traffic reduct...
Jason Zebchuk, Elham Safi, Andreas Moshovos
SPAA
1996
ACM
15 years 7 months ago
An Analysis of Dag-Consistent Distributed Shared-Memory Algorithms
In this paper, we analyze the performance of parallel multithreaded algorithms that use dag-consistent distributed shared memory. Specifically, we analyze execution time, page fau...
Robert D. Blumofe, Matteo Frigo, Christopher F. Jo...
JKM
2006
135views more  JKM 2006»
15 years 3 months ago
Learning from the Mars Rover Mission: scientific discovery, learning and memory
Purpose Knowledge management for space exploration is part of a multi-generational effort. Each mission builds on knowledge from prior missions, and learning is the first step in ...
Charlotte Linde
ICS
2009
Tsinghua U.
15 years 27 days ago
Refereeing conflicts in hardware transactional memory
In the search for high performance, most transactional memory (TM) systems execute atomic blocks concurrently and must thus be prepared for data conflicts. The TM system must then...
Arrvindh Shriraman, Sandhya Dwarkadas
TSP
2010
14 years 10 months ago
Optimization and analysis of distributed averaging with short node memory
Distributed averaging describes a class of network algorithms for the decentralized computation of aggregate statistics. Initially, each node has a scalar data value, and the goal...
Boris N. Oreshkin, Mark Coates, Michael G. Rabbat