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ICCAD
2008
IEEE
108views Hardware» more  ICCAD 2008»
16 years 1 months ago
FBT: filled buffer technique to reduce code size for VLIW processors
— VLIW processors provide higher performance and better efficiency etc. than RISC processors in specific domains like multimedia applications etc. A disadvantage is the bloated...
Talal Bonny, Jörg Henkel
ICASSP
2009
IEEE
15 years 11 months ago
Scalable distributed source coding
This paper considers the problem of scalable distributed coding of correlated sources that are communicated to a central unit. The general setting is typically encountered in sens...
Ankur Saxena, Kenneth Rose
151
Voted
CGO
2005
IEEE
15 years 10 months ago
Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache
Modern embedded microprocessors use low power on-chip memories called scratch-pad memories to store frequently executed instructions and data. Unlike traditional caches, scratch-p...
Rajiv A. Ravindran, Pracheeti D. Nagarkar, Ganesh ...
142
Voted
RTAS
2003
IEEE
15 years 10 months ago
Modular Code Generation from Hybrid Automata based on Data Dependency
Model-based automatic code generation is a process of converting abstract models into concrete implementations in the form of a program written in a high-level programming languag...
Jesung Kim, Insup Lee
SIGMETRICS
2008
ACM
128views Hardware» more  SIGMETRICS 2008»
15 years 4 months ago
Loss-aware network coding for unicast wireless sessions: design, implementation, and performance evaluation
Local network coding is growing in prominence as a technique to facilitate greater capacity utilization in multi-hop wireless networks. A specific objective of such local network ...
Shravan K. Rayanchu, Sayandeep Sen, Jianming Wu, S...