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» Worst case execution time analysis for synthesized hardware
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ASPDAC
2006
ACM
101views Hardware» more  ASPDAC 2006»
15 years 3 months ago
Worst case execution time analysis for synthesized hardware
- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on s...
Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-You...
ECRTS
2009
IEEE
14 years 7 months ago
Precise Worst-Case Execution Time Analysis for Processors with Timing Anomalies
This paper explores timing anomalies in WCET analysis. Timing anomalies add to the complexity of WCET analysis and make it hard to apply divide-and-conquer strategies to simplify ...
Raimund Kirner, Albrecht Kadlec, Peter P. Puschner
DDECS
2006
IEEE
146views Hardware» more  DDECS 2006»
15 years 1 months ago
Automatic Identification of Timing Anomalies for Cycle-Accurate Worst-Case Execution Time Analysis
Abstract-- Hard real-time systems need methods to determine upper bounds for their execution times, usually called worst-case execution times. Timing anomalies are counterintuitive...
Jochen Eisinger, Ilia Polian, Bernd Becker, Alexan...
SEUS
2005
IEEE
15 years 3 months ago
Measurement-Based Worst-Case Execution Time Analysis
In the last years the number of electronic control systems has increased significantly. In order to stay competitive more and more functionality is integrated into more and more p...
Ingomar Wenzel, Raimund Kirner, Bernhard Rieder, P...
CSREAESA
2003
14 years 11 months ago
Worst Case Execution Time Analysis for Petri Net Models of Embedded Systems
We present an approach for Worst-Case Execution Time (WCET) Analysis of embedded system software, that is generated from Petri net specifications. The presented approach is part ...
Friedhelm Stappert, Carsten Rust